1. Field of the Invention
Embodiments of the invention relate generally to semiconductor memory devices. More particularly, embodiments of the invention relate to multi-bit flash memory devices and memory cell arrays for the multi-bit flash memory devices.
A claim of priority is made to Korean Patent Application No. 2006-88705, filed on Sep. 13, 2006, the disclosure of which is hereby incorporated by reference in its entirety.
2. Description of Related Art
Semiconductor memory devices can be roughly classified into volatile and nonvolatile semiconductor memory devices. Volatile memory devices allow high speed read and write operations, but lose data when disconnected from an external power source. On the other hand, nonvolatile memory devices retain stored information even when disconnected from an external power source.
Because of their ability to retain stored data when disconnected from an external power source, nonvolatile memory devices are commonly used in applications where power is limited or may be lost unexpectedly. Some common examples of nonvolatile memory devices include masked read-only memory (MROM), programmable ROM (PROM), erasable and programmable ROM (EPROM), and electrically erasable and programmable ROM (EEPROM).
In general, it is difficult to update stored information in nonvolatile memory devices such as MROM, PROM and EPROM. However, EEPROMs can be efficiently erased and programmed through electrical means. As a result, EEPROMS are widely employed in applications such as portable electronic devices or system components requiring relatively frequent data updates.
Flash memory is one common form of EEPROM. Flash memory offers relatively high density data storage compared with many conventional EEPROMs, and as a result, flash memory can provide large amounts of data storage in subsidiary memory systems or in portable devices. Among flash memories, NAND-type flash EEPROMs, also called NAND flash memories, provide exceptionally dense data storage.
FIG. 1 is a memory block diagram illustrating a conventional flash memory device. Referring to FIG. 1, the flash memory device includes a memory cell array 10, a row decoder 20, and a page buffer circuit 30. Memory cell array 10 comprises a plurality of memory cell memory blocks. Each memory cell memory block includes a plurality of memory cell strings, referred to hereafter as “NAND strings”. Each NAND string comprises a plurality of floating gate transistors M0 through Mn−1 functioning as memory cells. As an example, FIG. 1 shows NAND strings included in a single memory cell memory block. Floating gate transistors M0 through Mn−1 in each NAND string are serially connected between a corresponding string selection transistor SST and a corresponding ground selection transistor GST.
The device of FIG. 1 comprises a plurality of word lines WL0 through WLn−1 and selection lines GSL and SSL arranged in rows and connected to memory cell array 10. Word lines WL0 through WLn−1 are driven by row decoder 20. The device of FIG. 1 further comprises a plurality of bit lines BL0 through BLm−1 arranged in columns and connected to memory cell array 10. Bit lines BL0 through BLm−1 are driven by page buffer circuit 30. Each memory cell in memory cell array 10 stores one or more bits of data.
Memory cells that store more than one bit of data are commonly referred to as multi-level cells (MLCs). Examples of multi-level cells are described in a variety of sources, including for example, U.S. Pat. Nos. 6,122,188, 6,075,734, and 5,923,587, the respective disclosures of which are incorporated by reference. To briefly explain the function memory cells in a flash memory device, FIGS. 2 and 3 show threshold voltage distributions representing different logic states in flash memory cells. In particular, FIG. 2 illustrates threshold voltage distributions for 1-bit, 2-bit, and 4-bit multi level cells and FIG. 3 illustrates threshold voltage distributions for 1.5-bit, 2.5-bit, and 3-bit flash memory cells.
From FIGS. 2 and 3, it can be seen that flash memory cells are able to store data using different threshold voltage distributions. For instance, as shown in FIG. 2, a flash memory cell is able to store 1 bit of data using two threshold voltage distributions, 2 bits using 4 threshold voltage distributions, or 4 bits using 16 threshold voltage distributions. Similarly, as shown in FIG. 3, the flash memory cell is able to store 1.5 bits of data using 3 threshold voltage distributions, 2.5 bits using 6 threshold voltage distributions, and 3 bits using 8 threshold voltage distributions.
A NAND string typically comprises 16, 32, or 64 memory cells. In other words, in memory block 10 shown in FIG. 1, “n” is typically equal to 16, 32, or 64. Accordingly, a NAND string comprising flash memory cells such as those illustrated in FIG. 2 can store 16, 32, 64, 128, or 256 bits of data. In other words, where each NAND string in memory block 10 comprises 16, 32, or 64 memory cells, each storing 1, 2, or 4 bits of data, memory block 10 can store 16, 32, 64, 128, or 256 pages of data, where each page of data corresponds to “m” memory cells connected to the same word line. Similarly, a NAND string comprising flash memory cells such as those illustrated in FIG. 2 can typically store 24, 40, 48, 80, 96, 160, or 192 bits of data. In other words, memory block 10 can store 24, 40, 48, 80, 96, 160, or 192 pages of data using flash memory cells such as those illustrated in FIG. 3.
Nowadays, most manufacturers of flash memory devices produce the flash memory devices with memory cells adapted to store 2n bits of data, where “n” is an integer greater than or equal to 0. Accordingly, product specifications for flash memory devices and control schemes for associated file systems are typically defined with reference to flash memory cells adapted to store 2n bits of data.
In general, program and read operations for NAND flash memory devices are carried out in page units. On the other hand, erase operations for NAND flash memory devices are typically carried out in units of several pages or entire memory blocks. As a result, where the number of pages in each memory block is not a power of two (2n), but rather is a number such as 48, 80, 96, 192 or 384, conventional control schemes may not achieve desirable results. Accordingly, in order achieve compatibility between conventional flash memory devices including memory cells adapted to store different amounts of data, an additional file system control scheme or flash memory organization may be required. However, unfortunately including such additional features increases the cost of manufacturing the devices.